An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs

One of the main causes of ESD failure, the Charged-Device-Model (CDM) current can cause a voltage build-up across Gate-Source junction of receiver MOS resulting in breakdown. An efficient and cost-effective solution is proposed to identify CDM risks in designs and further analyze the identified risks considering the full context of the design in Bulk-Silicon processes. First, simple risk topologies are used for recognition through a pattern identification engine. Those are then augmented with various risk analysis capabilities, to only highlight real risks, weeding out false violations.