ASIC Implementation of FIR Filter Using 16x16 Hybrid Vedic-Dadda Multiplier for ECG-Denoising

As technology is scaling, the contemporary world is achieving the demand of replacing the existing systems by their area and power compatibility. Electrocardiography (ECG) is a biomedical device that is considered as a fundamental tool in diagnosing cardiovascular diseases (CVDs). To build area and power-optimized biomedical devices that use basic blocks like multipliers, adders, filters, etc., need developed efficient basic blocks. This work proposes the design of a linear-phase low-pass FIR filter (LPFF), by employing a hybrid multiplier named the Hybrid Vedic Dadda multiplier. The LPFF is compared and proved to reduce area by 5.5%, power by 8.5%, delay by 2.2%, and saving EPT by around 9.5% compared with the existing Hybrid Vedic Wallace Tree Multiplier (HVWTM) FIR filter. The proposed FIR filter's efficiency is verified with Intel DSP Builder, followed by implementation and synthesis with the Cadence RTL compiler in 90nm technology.