Efficient Chip Design of Penta Linear Array Charge Coupled Device (CCD)

Charge coupled devices (CCDs) have historically played a crucial role in a variety of imaging and sensing tasks owing to their notable sensitivity, minimal noise, and impressive dynamic range. With technological progress, there is an increasing demand for CCDs with improved functionalities and efficiency to meet demands of various applications. One notable progression in CCD technology involves emergence of Penta Linear Array CCDs. This paper presents the design of a silicon-based CCD for space-based remote sensing in visible spectrum using Cadence Virtuoso software. The image sensor comprises linear five arrays, each linear array consisting of 6000 pixels. The pixel structure incorporates a 16×16 μm pinned photodiode, along with a storage gate, bias gate, transfer gate, and anti-blooming area. Each linear array is equipped with four readouts for charge-to-voltage conversion and amplification. The pixel array has been designed according to four poly and two metal layers. The clock fidelity simulations are performed using resistances and capacitances derived from the design layout in Cadence Virtuoso. The significant contributions of this paper lie in full chip CCD layout, encompassing subfield metal routing, device pad placement, and shield metal routing. The entire CCD chip design is thoroughly verified using design rule checks (DRCs), and subsequently generated a GDS file for fabrication.