Reliability of Tunneling Regime for Silicon on Insulator-Based Neuron

Low-power operations are essential for implementing large spiking neural networks (SNNs) in real-world applications. An area and energy-efficient demonstration of a functional liquid state machine (LSM) for spoken word detection using the band-to-band-tunneling (BTBT)-based neuron was proposed earlier. For a product-level demonstration of the BTBT regime operating chips, the variability and reliability of neurons emerge as noteworthy concerns for neuromorphic processors due to the potential implications for performance degradation over time. In this work, we characterize and compare the reliability of partially depleted (PD) silicon on insulator (SOI) transistors in the BTBT and on-regime ( ${I}_{\text {ON}}$ ) regimes. The drain current fractional degradation ( ${\Delta }{I}_{\text {D}}/{I}_{\text {D}}$ ) increases with an increase in voltage and thermal stress in the BTBT and ${I}_{\text {ON}}$ regime. The reaction-diffusion-drift (RDD) framework is used to estimate device degradation under operating bias conditions. At operating bias, a ~17% fractional degradation is observed in the BTBT regime operation for ten years, comparable to the degradation observed in the ${I}_{\text {ON}}$ regime. Finally, we analyzed the impact of device degradation on the SNN performance.