Simplified RSA Encryption Module for FPGA: A Comparative Analysis Between Kintex and Genesys Boards

This Verilog module encapsulates simplified RSA encryption in an FPGA design. With a default key length of 1024 bits, the module has clock, reset, and start signals to start encryption. Core functionality controls encryption using internal signals generated by the start signal. This presentation simulates encryption by increasing the internal state upon the start of signal activation. Although a placeholder for encryption logic, the output port outputs encrypted data depending on the internal state. The module provides a basis for FPGA-based RSA encryption, enabling hardware customization and integration. Comparison is done between Kintex and Genesys boards based on resource utilization, performance measures including throughput and latency, and power consumption. The implementation and optimization methodologies for each board may greatly affect these elements and their applicability for various applications and settings.