Towards Fine-grained Partitioning of Low-level SRAM Caches for Emerging 3D-IC Designs

Scaling on-chip memory capacity is one of the primary approaches to mitigate memory wall bottlenecks. Various 2.5/3D integration schemes, leveraging novel partitioning is being actively explored to improve system performance. However, fine-grained functional partitioning of memory macros is not widely reported. As SRAM scaling stagnates with emerging CMOS logic roadmap, we propose a partitioning of low-level (faster access) caches in 3D using an Array Under CMOS (AuC) technology paradigm. Our study focuses on partitioning and optimization of SRAM bit-cells and peripheral circuits, enabling heterogeneous integration, achieving up to 12% higher operating frequency with 50% leakage power reduction in the memory macros. Applied on a 64-bit mobile SoC CPU core, we achieve upto 60% higher energy efficiency compared to 2D baseline and 14% increase in operating frequency compared to standard memory-on-logic 3D partitioning scheme.