A 3.5 to 4.7-GHz Fractional-N ADPLL With a Low-Power Time-Interleaved GRO-TDC of 6.2-ps Resolution in 65-nm CMOS Process

This paper proposes a low-power design method and a low-noise phase offset calibration technique for a gated ring-oscillator time-to-digital converter (GRO-TDC), which normally consumes a large percentage of most all-digital phase-locked loop (ADPLL) power. A single coarse counter logic structure along with time-interleaved even/odd paths significantly reduces the complexity and speed of the TDC logic. The proposed TDC consumes only 0.44 to 24 mW for 0.077 to 24.42 ns of detection range. The multi-path GRO accelerates the oscillation speed and achieves approximately 6.2 ps of time resolution. The GRO-TDC shows –1.43 to 1.35 least-significant bits (LSB) of differential non-linearity (DNL) and –1.32 to 1.96 LSB of integral non-linearity (INL) over a 11-bit dynamic range (DR). The entire ADPLL including the proposed TDC has been fabricated in a 65 nm CMOS process and occupies 0.67 mm2 of active area. The prototype ADPLL consumes 12.22 mW from 1.2 V supply and the TDC consumes only 0.65 mW for a 50-phase offset code. A modified integrating structure in the subsequent digital loop filter (DLF) has been developed to mitigate dithering noise on
$V_{ctrl}$
code and the measured reference spur is –69.38 dBc at 3.6 GHz center frequency. The tuning range of the implemented ADPLL is 3.5 to 4.7 GHz by using 2-bit band switching and 5-bit coarse control, while maintaining low-
$K_{DCO}$
values to suppress in-band quantization noise. The measured root-mean-square (RMS) jitter is 0.94 ps and 0.99 ps at 3.6 GHz integer-mode and 3.60743 GHz fractional-mode respectively.