Self-Timed Circuit Emulation on FPGA

Field programmable gate arrays (FPGAs) serve as a convenient tool for prototyping and debugging developed digital circuits. Their circuitry is optimized for synchronous unit implementation. Computer-aided design systems for digital circuits on FPGAs are also focused on synchronous projects. However, one can also use FPGAs for prototyping self-timed (ST) circuits in the mode of emulating a single-stage representation of some logical and indication cells. The paper analyzes the ST circuit indication cell implementations on the FPGAs and proposes a technique for emulating ST circuits on typical FPGAs. The paper estimates a hardware redundancy of the ST circuit implementations on FPGAs and the results of prototyping an ST unit multiplying two operands with subsequent third operand addition and subtraction without intermediate rounding on the Intel Cyclone and Arria families FPGAs.