A new high-performance programmable delay line IC

A novel implementation of a programmable digital delay line based on a shift register for video applications is presented. An optimized register developed to reduce the power dissipation of the register files is described. A compromise between the power dissipation and area of the circuit is used to obtain high performance. The chip features a 20-MHz operating frequency and 200-mW power dissipation. This chip has been designed with a 1.2- mu m CMOS technology.<>