Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis

Probabilistic computing is a promising computational paradigm that harnesses the inherent stochasticity of devices to tackle problems that can benefit from stochastic-driven search. A probabilistic bit (p-bit), the workhorse of probabilistic computing, is popularly implemented using energy-efficient low-barrier nanomagnets, highly-scaled transistors, and unstable memory elements. These implementations are prone to process- and environmental-induced variations and aging-induced non-idealities. These non-idealities can manifest as unwanted bias in a p-bit and its incoming signals, impacting the figures of merit of probabilistic computing. For the first time, this work systematically investigates this aspect of probabilistic computing. First, we investigate the behavior of a non-ideal p-bit using an analytical model proposed in this work and corroborate the results using numerical computation. Then, we examine the impact of these non-idealities on the functionality and robustness of the probabilistic computing using Boolean logic implementation and image completion networks in the forward and backward modes of operation, respectively. For Boolean logic implementation, the weight matrix is found to be robust enough to allow p-bit network to retain its intended functionality despite non-idealities. Moreover, we show that there can be canceling effects of non-idealities, which can potentially be utilized in compensating reliability-induced degradation in a p-bit network. Additionally, using 1T-1MTJ-based p-bit implementation and SPICE simulations, we illustrate the applicability of the proposed model in analyzing and assessing the impact of non-idealities and process-induced variations on a p-bit network. We also demonstrate that statistical analysis techniques, such as Monte Carlo simulations, can help derive application-dependent constraints on the non-ideality of p-bits. These constraints will serve as critical design criteria for future p-bit implementations.