Low Power MAC Using Modified Booth Encoder

This research presents a novel, low-power, high-performance multiplier architecture that integrates a Modified Booth Encoder (MBE) with a Spurious Power Suppression Technique (SPST). Multipliers are critical components in digital systems, and optimizing their power efficiency and speed is essential. The MBE reduces partial product generation, improving speed and power consumption. To further enhance power efficiency, we introduce an SPST to eliminate unnecessary power dissipation caused by spurious transitions. The proposed design incorporates modules for MBE, SPST, partial product generation, and accumulation. Experimental results demonstrate the significant power reduction achieved through the combined use of MBE and SPST, making the proposed architecture suitable for power-constrained digital signal processing applications.