High-Speed and Area-Efficient Approximate Multiplier Using Truncation Technique

One of the most important arithmetic functional units in many applications is the multiplier. Large multiplications are often required for these applications, which adds up to a significant power consumption. With the use of pipelining, this project presents a pipelined-based approximation multiplier, improving performance. By utilizing previous research on an approximate compressor with great performance, the study tackles the computationally demanding nature of multipliers in applications that necessitate multiple calculations The proposed approximate multiplier helps error-tolerant systems by reducing key path delays. Adjustable to dynamically truncate partial products for various precision needs, the multiplier balances the trade-offs between area, power, and accuracy. A user-adjustable approximation multiplier with run-time accuracy and power adjustments is-included in the design, along with a high-precision 4-2 compressor. The performance of the experimental designs is-better than that of precise multipliers and non-pipelined system