High-Throughput Software-Defined LDPC Encoder and Decoder With x86-Based Data-Level Parallelism

In order to realize the high-throughput software-defined low-density parity-check (SD-LDPC) encoder and decoder for 5G communication systems, this paper presents various algorithm-software co-optimization techniques allowing advanced data-level parallelism. We first develop efficient mapping schemes to describe the contemporary 5G LDPC processing with recent x86 single instruction multiple data (SIMD) instructions. Then, the data rate of 5G SD-LDPC processing is remarkably improved by introducing SIMD-aware algorithm-level innovations, e.g., parallel efficient encoding, minimizing branch instructions, approximate check-node processing, and latency-oriented optimization. Compared with the state-of-the-art approaches, experimental results show that the proposed techniques successfully enhance the speed of encoding and decoding operations by 8.1 and 1.5 times, respectively, leading to the high-speed and fully-flexible software-defined radio (SDR) solutions for 5G systems.