Hardware-Efficient ECC Processor Design using Non-Homogeneous Split Hybrid Karatsuba Multiplier

Elliptic Curve Cryptography(ECC) is a distinct and efficient public-key cryptography method that balances security and performance well, with shorter key lengths. A primary component of ECC is the multiplier unit which performs scalar multiplication operations. This work implements a hardware-efficient ECC design with non-homogeneous M-Term Hybrid Karatsuba multiplier structure for
$\text{GF}(2^{233})$
Montgomery Point multiplication, and is further compared with the state-of-the-art (SOTA) ECC processors. The proposed design was implemented and verified on FPGA board (Zynq ZU19EG) and also synthesized using 45 nm technology library on the Cadence-Genus tool. Overall two variants of ECC designs engineered with eight individual polynomial multipliers were evaluated. The M-Term Non-Homogeneous Karatsuba Multiplier (MNHKA) and M-Term Non-Homogeneous Overlap-free Karatsuba Multiplier (MNHOKA) incorporated ECC processors exhibited the best hardware-efficient designs on FPGA and on silicon, among all the variants investigated. LUT savings of 34.74% with Figure-of-merit (FoM) enhancement of 86.70% was characterized for MNHKA designed ECC processor in FPGA over SOTA design. On silicon, MNHOKA incorporated ECC exhibited maximum footprint savings of 55.86%, and highest ADP gain of 53.93%, incurring comparable delay when compared with SOTA designs. The novel and efficient ECC accelerator designs to enhance the reliability of the hardware security units, are made freely available for further usage.