Compact Multiplexer Design with Multi-threshold Ferroelectric FETs

Ferroelectric FETs (FeFETs) are promising emerging nonvolatile memory devices due to their attractive features such as CMOS compatibility, non-volatility, multi-level cell (MLC) storage capability, and programmable threshold voltage. The majority of research efforts thus far have focused on exploring FeFETs for applications in memory and logic gates. In this work, we present a novel multiplexer design with FeFETs. Multiplexers control data flow in any integrated circuit (IC) and are major components in both ASICs and FPGAs. We leverage the programmable multi-threshold states of the FeFETs to design a compact multiplexer with a lesser number of transistors and with reduced intermediate stages compared with CMOS counterparts. The proposed design demonstrates that a significant reduction in number of transistors can be achieved by constructing a MUX utilizing multi-threshold transistors based on a pass-transistor configuration in the design. Our analysis shows, using 4 threshold voltages, the proposed design saves 2 transistors (14.29%) on 8:1 MUX, and 6 transistors (20%) on 16:1 MUX. The number of stages in the MUX tree decreases from 3 to 2 for 8:1 MUX, and from 4 to 2 for 16:1 MUX.