A 3-Segment Interpolating String DAC with Low-Cost Built-In-Self-Test Capabilities

This paper presents a 3-segment interpolating string DAC with low-cost built-in self-test (BIST) capabilities. Through rigorous mathematical analysis, we establish explicit design constraints necessary to guarantee the linearity of the segmented DAC in the absence of device non-idealities without the use of buffer amplifiers. In addition, a BIST algorithm is proposed to estimate the INL of the proposed DAC. We validate the proposed design using simulation results of a 14-bit version of the DAC designed in TSMC 180nm technology. The BIST testing scheme is implemented in MATLAB, using a SAR ADC model. Simulation results indicate an INL estimation error of less than 0.6 LSBs for the 14-bit DAC and 14-bit ADC across 200 Monte-Carlo simulations.