Most Significant Digit First Multiply-and-Accumulate Unit for Neural Networks

The Multi-layer Perceptron (MLP) is a feedforward neural network commonly applied in various artificial intelligence applications. Although fully parallelism can be exploited in this type of network to speed up computation in hardware implementations, challenges related to cost and energy consumption must be addressed. On inference, where the network is already trained, serial computations offer low-cost implementations, though introducing a higher potential delay. In this paper, we propose a serial multiply-and-accumulate (MAC) unit designed to perform computations based on the most significant digit-first approach, providing a balanced solution. This MAC unit is incorporated into a pre-trained MLP architecture with the MNIST dataset. Hardware-based inference using the proposed MAC unit achieves high accuracy, up to 97.4 %. This design results in significantly less circuit area and energy per neuron compared to fully parallel MLP. The synthesis of MLP designs is performed using the Synopsys Design Compiler with 45 nm CMOS technology. To further assess the efficiency of the proposed MLP design, a comparative evaluation is investigated with state-of-the-art MLPs. Results show that the proposed design leads to better delay, area-delay product (ADP), and energy while maintaining high accuracy, compared to current designs found in the technical literature.