Design of Multiplier Circuit Based on Signed-Digit Hybrid Stochastic Computing

In this paper, a signed-digit hybrid stochastic computing (SD-HSC) with bipolar format is first proposed and its multiplier of the CMOS circuit is implemented. The SD-HSC proposed uses a new number representation method called signed-digit hybrid stochastic number (SD-HSN) which combines the two-line bipolar stochastic number and the signed-digit number system. The properties of basic SD-HSC circuits including generation, addition, and multiplication are designed and demonstrated. The multiplier of SD-HSC is implemented based on a standard 40-nm CMOS process. The results of the proposed SD-HSC multiplier show its advantage in hardware cost and power consumption over conventional signed-digit number multipliers and its high accuracy, high efficiency, and low latency compared to the classic stochastic computing methods. The high computation performance of an SD-HSC multiplier is highly increased thanks to the redundant HSC circuit.