Ultra-Small Area, Highly Linear, Modified All Mosfet Digital-to-Analog Converters with Novel Real Time Digital Calibration Algorithm

This paper introduces the design of a highly compact all MOSFET current steering Digital-To-Analog Converter (DAC) with redundancy. We propose a technique that utilizes redundancy and topological modifications to achieve a DAC with improved linearity, and significantly reduced area. With this technique, we can implement a compact DAC without requiring stringent matching requirements (N-9 bits). Additionally, we present a novel calibration algorithm that is low latency, memory and computationally efficient. This algorithm is capable of calibrating negative jumps as well as large positive jumps, which were previously considered non-calibratable errors. As a result, the need for the use of sub-radix DACs to eliminate positive jumps is alleviated. We validate our circuit through simulations conducted in TSMC 180nm. Post-calibration results demonstrate that the design achieves an impressive 14-bit integral nonlinearity (INL) and differential nonlinearity (DNL) of ±0.3LSBs and ±0.5LSBs, respectively, despite being designed with only a 5-bit performance matching requirement.