An 8-bit 1 MS/s Low-Power SAR ADC with an Enhanced EPC for Implantable Medical Devices

This work represents a low-power 8-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter that employs an enhanced Edge-Pursuit Comparator for Im-plantable Medical Devices. SAR ADC is immensely recognized for its straightforward architecture, low power consumption, and extensive range of applications. SAR ADC's performance relies on the comparator's accuracy, energy efficiency, resolution, and speed. Hence, designing a high-speed, low-power, energy-efficient comparator is crucial for SAR ADC architecture. A low-power, 8-bit charge re-distribution SAR ADC architecture with an enhanced high-speed Edge-Pursuit Comparator is designed and simulated in Cadence Virtuoso 180 nm UMC CMOS technology, operating at a supply voltage of 1.8 V and a sampling frequency of 1 MS/s. From the simulation results, it is concluded that the proposed 8-bit SAR ADC with an enhanced EPC consumes power of about 40.5 µW. It achieves a DNL of 0.004 LSB, an INL of 0.015 LSB, and dynamic performance characteristics with a simulated SNDR of 48.15 dB, an SFDR of 55.52 dB, and an ENoB of 7.7 bits, respectively, for a 50.781 kHz input signal at 1 MS/s sampling frequency. Moreover, corner analysis and Monte-Carlo simulation are performed, and dynamic performance characteristics are examined for various input frequencies around the Nyquist rate.