Natural Language Processing Meets Hardware Trojan Detection: Automating Security of FPGAs

The inherent runtime reconfiguration capability of field programmable gate array (FPGA) has been a key feature for deployment in various application scenarios, such as data centers, cloud computing, and edge computing, among others. In such applications, reconfiguration is achieved via remote access, which allows multiple users to utilize FPGA resources concurrently and modify the configuration bitstream. An adversary can exploit the accessibility of the configuration bitstream to insert a hardware Trojan (HT) into the FPGA, thereby creating a critical security vulnerability. Since the HT is designed to remain dormant to avoid detection, it can bypass conventional verification and vali-dation techniques. However, any HT inserted in a configuration bitstream must leave a trace even if it is dormant. This paper proposes a supervised learning method using a deep, recurrent neural network (RNN) algorithm to identify such malicious configuration bitstreams in FPGAs. By analysing the patterns present in the bitstream, the proposed method is able to identify any anomalies present in the implemented design. Our method is applied to three ISCAS 85 benchmark circuits of various sizes and topology, implemented on a Xilinx Artix-7 FPGA. Our experimental results showed a maximum accuracy of 93% in detecting HT in bitstreams.