Compact 6T-SRAM Using Bottom-Gate Transistor in FD-SOI Process for Monolithic-3D Integration

Monolithic three-dimensional integrated circuits (M3D-IC) have gained attraction as a promising alternative to conventional IC design to preserve Moore's law. The interconnections between the top and bottom layers in M3D-ICs are facilitated through the Metal interlayer via (MIV). Previous works on M3D-IC show that up to
$10^{8}$
MIVs pass through the top substrate creating an overhead since these MIVs occupied active device region areas in the top substrate. On the other hand, on-chip SRAM has become an important component in modern IC design. This area overhead brought by MIV has become significant for SRAM cell design in M3D-IC. Towards this, we propose a bottom gate transistor on the top-layer, which requires one extra lithography step. With bottom-gate transistor utilization, there is no MIV overhead for SRAM cell design in M3D-IC implementation. Simulation results suggest that the proposed approach can reduce the SRAM cell area and leakage current
$\mathbf{I}_{\mathbf{leak}}$
by 21 % and 12.45% compared to the conventional SRAM cell implementation in M3D-IC. In addition, the noise margins of the SRAM cell also improved for the bottom-gate transistor-based approach to the conventional SRAM cell design.