High-Bandwidth and Energy-Efficient Memory Interfaces for the Data-Centric Era: Recent Advances, Design Challenges, and Future Prospects

Currently, we are living in a data-centric era as the need for large amounts of data has dramatically increased due to the widespread adoption of artificial intelligence (AI) in a variety of technology domains. In the current computing architecture, the memory input and output (I/O) bandwidth is becoming a bottleneck for improving computing performance; therefore, high-bandwidth memory interfaces are essential. In addition, the high power consumption of data centers to edge AI devices will lead to power shortages and climate crises in the near future; therefore, energy-efficient techniques for memory interfaces are also important. This paper presents contemporary approaches to improve I/O bandwidth, such as increasing the I/O pin count and data rate/pin, and to save energy in memory interfaces. However, there are still some design challenges that require further improvements. Therefore, various design challenges and problems to be solved are discussed, and future perspectives, including chiplet and die-to-die interfaces, are presented. Based on various research and development efforts to overcome the current limitations, the technological paradigm shift and related industries are expected to advance to the next level.