Functional Verification of Arithmetic Logic Unit and Instruction Fetch Unit of a 32-bit RV321M ISA based RISC-V Processor

Verification is a pivotal process in the design life cycle of integrated circuits, ensuring the functionality aligns with the chosen architecture. This paper focuses on the verification of the Arithmetic Logic Unit (ALU) and Instruction Fetch Unit (IFU) of a processor using Universal Verification Methodology (UVM). By adopting a simulation-based approach, this project aims to enhance confidence in the conformance of the ALU and IFU design to their specifications. Through this project, we aim to establish a robust verification methodology using UVM for validating the ALU and IFU components in a processor design. The adoption of UVM promises to enhance verification quality, scalability, and reusability while ensuring adherence to processor specifications.