Novel Methodology of reduction in PDP for digital designs using FGMOS and LECTOR techniques

As device dimensions diminish, the static power i.e. leakage power, experiences an increase due to the implications of short channel effects. This paper proposes a novel methodology, for reducing both leakage and dynamic power consumption by using Floating Gate MOS (FGMOS) and Leakage Control Transistor (LECTOR) based circuit. The main idea is to implement the Pull Down Network (PDN) or Pull Up Network (PUN) by FGMOS and putting two leakage controlled transistors (LCTs) in between the PDN and PUN. The proposed technique reduces the leakage i.e. short-circuit currents by using Lector technique and by using FGMOS the supply voltage requirement of the circuit is reduced. Using the proposed technique, CMOS static gates namely logical inverter, NAND and NOR, are designed and simulated using cadence virtuoso, in 90-nm CMOS technology. Simulation findings obtained with 0.5V power supply voltage indicate a noteworthy reduction in the Power–Delay Product (PDP) for inverter, NOR, and NAND gates compared to their other counterparts.