Ascon-128 with PicoRV32 for Authenticated Encryption at IoT Edgeon FPGA

Open source RISC-V based SoC is an essential component required for the widespread development and deployment of secure and privacy enhanced IoT edge devices. PicoRV32 has been identified to be the suitable core for the development of RISC-V based SoC. The security features required by aSoC that is used as a component of an edge device are encryption-decryption, authentication, authorization, digital signatures, etc. In this paper, the light weight authenticated encryption-decryption module Ascon -128, which is the NIST finalist, has been integrated with PicoRV32 and implemented on FPGA. This is an important step towards developing a secure RISC-V SoC. The relative performance evaluation has been carried out by integrating PicoRV32 with AES GCM-128 as well. Since Ascon has been chosen over AES GCM-128 for edge devices, it is crucial to see that the advantages are maintained in the implementation even after integration with PicoRV32 using AXI4-lite interconnect, as a proof of concept. The post implementation results show that Ascon -128 needs resources much lesser than that of AES GCM-128 in the range of operating frequencies between 50 MHz to 600 MHz. Its maximum operating frequency is however lower by about 20% as compared to AES GCM, while maintaining its power advantage of around 3%.