Improve power control action during Inverse Temperature Dependency in hybrid core architecture

The advanced microarchitecture design philosophy prioritizes performance, efficient power management, and thermal output control, with a focus on hybrid computing cores and integrated IP blocks like memory, high-speed I/Os, Cache-Coherent-Fabric, Image Processing Unit, etc. Each IP has multiple Digital Thermal Sensor (DTS) diodes to monitor temperature. These IPs and their diodes are placed micrometers apart inside an SoC. According to the Inverse Temperature Dependency (ITD) effect, transistors slow down as temperature decreases for supply voltages below a critical limit, requiring increased voltage. ITD is an algorithm that involves voltage compensation based on temperature and the minimum voltage (Vmin) needed to switch on a transistor. As the SoC runs colder, more voltage is needed, increasing power consumption, and causing the SoC to hit its power limits (PL1/PL2) at lower temperatures, resulting in performance loss. The proposed solution could improve performance per watt by 5% to 10%, especially at lower temperatures and when exiting a low-power state. The core with the highest DTS temperature will wake up first, preventing hot cores from hitting PL1/PL2 early.