Split-Length Compensation LDO with Low Quiescent Current

An LDO with an internally compensated super source follower and adopted Split-Length Compensation technology indirectly compensates loop stability is proposed. The super source follower is used to reduce the output impedance of the LDO, enhancing its carry-under-Ioad capability. The loop is then converted to a multi-zero-pole system through techniques such as Split-length compensation, enabling the LDO to achieve stability and reliability under varying loads. The LDO proposed in this study was designed using a 110nm CMOS process. Simulation results indicate that the output voltage is 1.85 V when supplied with 3.3 V and TT process angle-the LDO with a low quiescent current of 57μA. The load regulation is 0.00769 mV/mA, and the line regulation is 0.48 mV/V. The system demonstrates optimal phase margins and circuit stability under all operational conditions.