An SAD architecture Verilog based for pattern matching

With the increasing importance of data security, encryption methods like advanced encryption standard (AES) have become pivotal in safeguarding sensitive information. However, the vulnerability of AES keys to side channel attacks (SCA) poses a significant threat. This paper proposes a novel approach using sum-of-absolute-difference (SAD) architecture for pattern matching, implemented on field-Programmable gate arrays (FPGAs) using Verilog. The SAD architecture, integrated with absolute difference (AD) architecture, offers an efficient solution for detecting the onset of AES computational processes without relying on victim signaling, crucial for real-world scenarios. The architecture's functionality and performance were validated through simulations using Vivado software, demonstrating its efficacy in detecting data stream similarities, with potential applications in embedded systems.