High Performance 2-Dimensional Systolic Array Design for Edge AI Accelerator

In the last decade, deep learning has surged in importance and application, often surpassing domain experts in prediction accuracy within short timeframes. However, its computational efficiency relies on complex algorithms, demanding significant resources. This paper addresses this challenge by integrating optimal parallel computing, data flow optimization, and tiling techniques to design AI accelerator processing elements. We validate these techniques by implementing the LRCN model using TSMC 40nm technology. Compared to prior research, our method achieves a 30% improvement in gate count for the same AI model, highlighting its advantages for edge AI applications.