Efficient DSP Equalization Algorithm and Architecture Designs for High Speed Serial Links

An efficient channel equalization algorithm and its associated parallel architecture design for a 10 Gbps serial link receiver is presented. Transmission via PAM-4 signaling across a long-reach channel experiencing over 36dB attenuation and severe inter-symbol interference (ISI) is assumed. The proposed equalizer comprises a feed-forward equalizer (FFE) and a decision feedback equalizer (DFE) to respectively mitigate pre-cursor and post-cursor ISI. Simulations are first conducted to determine the optimal filter orders for FFE and DFE. Design techniques such as parallel predictive branch slicer (PPBS) and delay relaxation are employed to facilitate parallel computing of recursive loops in DFE and coefficient adaptation. Simulation results indicate that, the proposed parallel and relaxed adaptation scheme can converge in just 40 µs in the training phase and the bit error rate in transmission phase is less than 10^-6. Finally, a 16-way parallel computing architecture operating at 312.5 MHz is developed to meet the 5GHz baud rate requirement.