Experimentally Exploring the Performance of MOSFET Devices at Deep Cryogenic Temperatures

This study investigates commercially available 180 nm CMOS devices under deep cryogenic conditions, focusing on both short (180 nm) and long (600 nm) channel nMOS devices at temperatures down to 3.2 K. We meticulously measured key parameters including threshold voltage (V
th
), carrier mobility (μ
n
), subthreshold slope (SS), on-current (I
on
), and off-current (I
off
). Notably, as temperatures decreased, V
th
, I
off
, and SS values declined, while I
on
and μ
n
exhibited an increase. A notable observation was the dual Z
t
values for the short channel device, aligning with the significant rise in series resistance post carrier freeze-out at 77 K. Our results provide a foundational understanding for the extraction of compact model parameters, crucial for cryogenic CMOS simulation and circuit design. For short channel devices, V
th
evolved from 0.6 V at room temperature to 0.85 V at 3.8 K, carrier mobility increased from 200 to 400 cm2/V2s, and SS improved from 90 mV/dec to 20 mV/dec. Conversely, long channel devices, measured from 113 K to 3.2 K, showed V
th
alteration from 0.60 V to 0.64 V, mobility enhancement from 833 to 1220 cm2/V2s, and SS improvement from 30 mV/dec to 10 mV/dec.