Design and Optimization of a 3.4 MHz, 3-Stage Current-Starved Ring Oscillator

The design of a 3-stage Current Starved Ring Oscillator[CSRO] is presented in this work. The suggested work contains a method for minimizing frequency[freq] variances across all Process Voltage Temperature (PVT) parameters, with power consumption of 24.45μW at 27°C. A large N-mos is used in the biasing circuit to reduce frequency changes across temperature and supply voltage. Nearly 7% and up to 3% frequency variation is noticed across power supply voltage and temperature variations respectively. The voltage biasing circuit ensures that variances are kept to a minimal across all process corners.About 2.5% frequency variation has been observed over various process corners. The simulation of circuit is carried out using Cadence Virtuoso UMC 180nm CMOS technology. The design operates at 3.4MHz with a supply voltage of 1.8V.