Hardware Accelerator for Edge Detection

This is a development of configurable hardware accelerator for image processing that enhances edge detection. With such features as blurring, sharpening, vertical and horizontal embossment and also with the applied Canny edge detection – this constitutes the core function of this accelerator. One of the key characteristics in this novelty involves the hardware acceleration that considerably boosts operations such as NMS and hysteresis through parallelism. The approach dramatically decreases the time required for processing and demonstrates the effectiveness of hardware acceleration in handling the imaging system. The adaptive thresholding in this project improves on standard thresholding that has been traditionally used in edge detection with superior flexibility and performance. To improve the speed more, the image is partitioned in three sections and each section undergoes processing at the same time in distinct ‘always’ blocks indicating the potency of parallel processing for cut-down time. Another way in which the project’s effectiveness is verified are through comparisons between the MATLAB and Verilog implementations, where it is observed that Verilog is more effective than the former alternative for being fast. It is observed that it takes only 33,600 clock cycles for parallel execution while sequential takes about 100,352 clock cycles, implying a 33.4% better processing time.