Implementation and Analysis of Hardware Interrupts, Including the Handling of Prioritised Interrupts

The communication system within a System on Chip (SoC) is a crucial component, encompassed by the on-chip bus. This communication system is expected to exhibit flexibility by providing attributes such as low power consumption, higher bandwidth, low latency and efficient routing capabilities. In the SoC architecture, dynamic allocation of paths from one block to another is a fundamental requirement. However, challenges arise when multiple blocks need access to the same resource simultaneously, resulting in contention. To address this issue, arbiters are employed to resolve conflicts and ensure that only one block can access the resource at any given time, based on priority levels. Various arbitration algorithms have been proposed to tackle this challenge, including daisy chain arbiters, round-robin arbiters, binary tree arbiters, and others. In this research the Daisy chain and Parallel priority interrupt designs are implemented and analysed which is a part of future on-chip buses of globally asynchronous locally asynchronous or globally asynchronous locally synchronous SoCs.