Design and Implementation of Braun Multiplier using Verilog: Review

Multipliers & Adders Signal processing and Digital Signal Processing (DSP) systems require multilayer components. Carry-Save multipliers & BW multipliers both use parallel architectures and are commonly used for positive & negative number multiplication. The design & implementation of modified BM (Braun Multiplier) for positive number multiplication with an emphasis on speed, power usage and physical area efficiencies. We use the Xilinx tool to verify the multiplications using Verilog. The considerations are: FPGA based instrument checking and use of Verilog-VHDL to implement the code. These adders are incorporated into the multiplier design. A significant result of this study is that modified BM & BW multipliers deliver improved performance while reducing power consumption and reducing physical area.