Ternary SRAM Cell Designs for Next-Generation: A Comprehensive Investigation of 6T, 8T, and 10T Designs

Ternary logic is popular where it uses logic levels of 0, 1 and 2 instead of using the old binary logic structure. Due to this, it has grown to be very popular method in many applications. It is used in applications which focuses on high density data processing and also to obtain lower power consumption. The design of this SRAMs poses lot of challenges and there is a high demand for robust and optimized memory units. This work concentrates on overcoming the problems of higher power consumption that is found in traditional SRAM cells. It focusses on the comprehensive study if 6T, 8T and 10T SRAM cells. Through this study, the performance metrics are analyzed for power consumption and R/W efficiency. The results obtained shows the lower consumption of power and improved R/W efficiency.