Analysis of 8x8 Bit Various Multiplier Using Look-Up Table and Implementation in Fir Filter

In VLSI, the usage of multiplier in hardware for designing and implementing it in an application. In this paper the comparison of various 8x8 bit multipliers, including the Booth, Wallace tree, and binary multipliers, using look-up tables, or luts, in order to satisfy requirements related to performance and power usage. These elements are essential for determining which VLSI design is the most efficient. We have looked at the propagation delay and power dissipation. The propagation delay and power dissipation of our developed clock logics are minimal, according to the simulation results. When it comes to filters, the wallace tree multiplier works better with FIR filters. To generate schematic representations of the multipliers and obtain time, speed, and area characteristics, verilog code is implemented using the Xilinx ISE tool. MATLAB software is then employed to implement the FIR filter.