Implementation of an Optimized AXI using Verilog

Optimization of Throughput and Delay is a crucial need in any SoC system. In order to achieve an appreciable performance in the exchange of data between the components of a AXI(advanced eXtensible Interface) Protocol is widely used to facilitate the communication between functional blocks of SoC systems. AXI (advanced eXtensible Interface) protocol is a high – speed standard which assists in transfer of multiple data items between source (master) and destination (slave). Major signals which are used in AXI are "Valid", "Ready" and "Response". After completion of a transaction successfully to the slave, master can proceed with its next burst of transaction only after getting a feedback from the slave which indicates its readiness to accept next transaction. In most of the cases, master has to wait for the response from the slave thereby creating a delay in the operation affecting the overall Performance of the system. In order to address the issues pertaining to the delay, we have proposed an AXI model which employs a counter that automatically decrements its value after completion of every single successful transaction to the slave. The master can proceed with its next transaction when the counter value decrements to zero without waiting for the response from slave.