Debugging Method for Segmentation Faults Based on Hardware-Software Co-Analysis for Processor Verification

Verifying CPU chips is a highly challenging task due to intricate hardware design and complex operating system software. Identifying and debugging software execution errors within an operating system environment can be time-consuming, sometimes taking several months to resolve. When running a program in an operating system environment, a segmentation fault is standard error that occurs. In the past, only the software aspect of this issue was analyzed. However, this paper delves into the mechanism of segmentation fault from both software and hardware perspectives. It presents a segmentation fault flow view from the software and hardware coordination perspective and proposes two methods for debugging segmentation faults from both hardware and software perspectives. To validate the effectiveness of these methods, an experimental environment was built based on the open-source RISC-V processor C906. Experimental verification was conducted on common segmentation fault scenarios like an invalid page table and page read/write permission mismatch. The experimental results demonstrate that the proposed methods can acquire the exception cause, physical address, and stack information of the segmentation fault, effectively accelerating the debugging of the segmentation faults.