Test Method for Interlaken Interface Based on DRP

As a new generation of high-bandwidth scalable inter-chip communication protocol, the Interlaken protocol has excellent performance and flexibility in data transmission. It provides reliable and efficient communication for high-speed data transmission between different types of chips. At the same time, it also brings new opportunities and challenges for the Interlaken protocol test. Aiming at Built-in Self-Test (BIST), which has the problem of long test time due to more configurations in high-speed flexible interfaces, this article proposes an Interlaken test method based on dynamic reconfiguration port (DRP). The DRP in the Field Programmable Gate Array (FPGA) is used to reconfigure of the Interlaken interface in the test dynamically, instead of configuring the entire FPGA. This effectively reduces the number of FPG A configurations and shortens the configuration time in the test. By applying this method to the BQRVU9P FPGA manufactured by Beijing Microelectronics Technology Institute, the bit file generation time and configuration time are reduced to $1 / 32$ and $1 / 40$ of the BIST, respectively.