Multiple Dielectric Isolation Layer to Improve Programming Interference in 3D Charge-Trapping NAND Flash Memory

In three-dimensional (3D) NAND flash device, the spacer length decreases as the number of stacks increases in order to achieve high density and small size. As the spacer size of the device decreases, the interference problem between neighboring cells becomes more severe. To effectively solve these problems, methods have been proposed to replace spacer materials in 3D NAND device with low dielectric constant materials. In this work, we observe the pass-gate voltage ($\mathrm{V}_{\text {pass }}$) interference characteristics of various single dielectric and multiple dielectric spacers during programming. An isolation layer structure that splits the charge trapping layer is proposed in this paper. Furthermore, the performance improvement can be achieved by the high dielectric constant/low dielectric constant/high dielectric constant multilayer dielectric isolation layer structure. Based on this, the SiO 2 -Air-SiO2 (O-A-O) multiple dielectric isolation layer structure is proposed to improve the $V_{\text {pass }}$ interference characteristics. Improving the program characteristics of 3D NAND flash memory by the proposed structure will help to increase the reliability of the memory device.