Memory Effects Mitigation in Power Amplifiers through Envelope Impedance Optimization in the Collector Bias Network

In pursuit of enhancing transmitter linearity under broadband signal excitation, this paper introduces an analytical approach for investigating the memory effect of power amplifiers. A two-stage Doherty power amplifier based on gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) is used to validate the proposed theory. When driven by a 80 MHz 64-QAM modulated signal with peak-to-average power ratio (PAPR) of 6.8 dB, the doherty power amplifier realizes lower than -50 dBc adjacent channel leakage ratio (ACLR) after digital predistortion at 3.5 GHz.