A Compact 15–35 GHz 3-bit True-Time Delay Circuit Using 65-nm CMOS

A compact 3-bit switched-line true-time delay (TTD) circuit using a new combined delay network is proposed to achieve a flat delay response in 15–35 GHz. The new combined network is consist of two different coupled all-pass networks (CAPN) using delay-compensation technique. Two single-pole double-through (SPDT) switches and two double-pole double-through (DPDT) switches are used to realize switching eight delay states. This circuit can provide a delay of 40.6 ps with a resolution of 5.8 ps. The average insertion loss ranges from 7.4 dB to 10.7 dB, and the return loss is lower than -14 dB over 15–35 GHz. The RMS delay error and gain error are less than 1 ps and 0.6 dB, respectively. The chip area of this TTD circuit is $0.92\times 0.3$ mm 2.