Ultra-Low Dark Count Rate SPAD Fully Integrated in a 180 nm High-Voltage CMOS Process

A novel structure of a single-photon avalanche diode (SPAD) fabricated in a commercial
$\boldsymbol {180}$
nm high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) process is presented. Device performance in terms of dark count rate (DCR) and photon detection probability (PDP) is compared to a previously published design fabricated as a reference on the same die. We find that the new structure exhibits a DCR of
$\boldsymbol {0.11}$
Hz/
$\boldsymbol {\mu }$
m
$\boldsymbol {^{2}}$
at an excess voltage of
$\boldsymbol {5}$
V, which is among the lowest ever reported in a foundry CMOS process, and more than
$\boldsymbol {3}$
times lower with respect to the reference device. Moreover, the new structure shows a PDP/DCR ratio higher by up to a factor of
$\boldsymbol {4.2}$
compared to the reference device. The reasons underlying the differences in DCR and PDP between the two structures are explained using technology computer-aided design (TCAD) simulations. The novel device is demonstrated as promising for the design of low-cost SPAD array imagers, particularly in low-noise applications.