An Approach to Enhance the Efficiency of RISC-V Verification Using Intelligent Algorithms

As the complexity and scale of processor design increases, the significance of verification in the chip design process also expands. Nevertheless, conventional UVM verification techniques are encountering difficulties in meeting the increasing requirements, leading to extended processing durations, decreased coverage, and possible neglect of design flaws. This work focused on addressing these challenges by specifically examining RISC-V verification and implementing genetic algorithms to enhance the production of test vectors within the current UVM verification environment. Experiments have shown that this approach outperforms limited random verification in terms of speed in achieving the specified coverage targets. Our verification framework successfully achieves the objective coverage while reducing the utilization of test vectors by approximately 30.76%, compared to the random testing verification approach. Hence, this approach has the potential to enhance the efficiency of verification and conserve resources, thus mitigating the aforementioned issues.