Error Compensation based Approximate Booth Multiplier with Improved Booth Encoder and Low Complexity Compressor

Approximate multipliers reduce energy consumption in image processing by simplifying circuits, thereby introducing output errors. In this paper, three approximate Booth multipliers, including CABM1(Configurable Approximate Booth Multiplier 1), CABM2, and CABM3, are proposed by designing a booth encoder based on the value replacement of the Karnaugh map to reduce gate count. Then, new approximate compressors are presented for CABM2 to compensate for errors produced by the proposed booth encoder. Next, based on CABM2, the required resources of CABM3 are further reduced by introducing an OR gate. The output approximation of proposed multipliers is adjustable by configuring the number of applied approximate encoders. The exhaustive simulation and FPGA hardware implementation results show that compared with previous multipliers, CABM1 achieves a 41.7% reduction in MaxED (maximum error distance). Also, the NMED (Normalized mean error distance) for CABM2 decreases by 51.8%. Additionally, CABM3 reduces 51.1% NMED. Finally, the image multiplication results show that the PSNR reaches around 32dB, 2dB higher than previous designs; with SSIM remaining above 98%.