A Strategic Approach to Enhancing INL Performance in 10-Bit MOS-Based R-2R DACs through Area Allocation

This paper presents an approach to improving the Integral Non-Linearity (INL) performance of a 10-bit digital to analog converter (DAC) by strategically allocating area. We propose a methodology that improves matching performance by allocating varying areas to cells in the DAC structure based on their individual impact on the INL metric. Simulation results conducted in a TSMC 180nm process validate the effectiveness of our area allocation strategy, as a 10-bit DAC achieve 15.3% and 16.7% improvement in the INL when 18µm
²
and 27µm
²
area is reduced from LSB and allocated to MSB respectively. The DNL and ENOB also improved by 6.9% and 3.5% respectively.