Implementation of High Q and Low Cost 3D Inductor Embeded in Polyimide

As we enter the post-Moore era, the demand for miniaturization and high performance in chip systems is growing increasingly. This paper is dedicated to enhancing the electrical performance of inductors while reducing their size and improving integration. In this study, polyimide (PI) is selected as the substrate material, and photolithography is utilized to create vias. Compared to traditional silicon or glass substrates, the PI substrate not only provides a higher quality factor but also simplifies the manufacturing process and reduces production costs. However, planar inductors face dual limitations of space and performance in achieving high inductance density, leading to their occupation of a larger area on the chip. In contrast, 3D inductor technology, with its higher inductance density, emerges as the preferred space-saving solution. This research employs HFSS software to construct a 3D inductor model and simulates the performance of glass-based, silicon-based and PI-based inductors in comparison. By adjusting the aspect ratio, the height and the width of the RDL (Re-Distributed Layer), an in-depth simulation and analysis of their effects on inductance (L) and quality factor (Q) are conducted, with the aim of proposing a high-Q inductor structure. The simulation results show that when the diameter of the via is 20µm and the aspect ratio is 1: 5, the inductance density of the 3D inductor is 14.4 nH/mm2, and the peak value of Q is 43.62. It is worth noting that the PI-based inductor slightly outperforms the glass-based inductor in terms of quality factor, and the Q value increases with the increase in RDL height and width. The morphology of the etched surface and adhesive removal after laser debonding exhibits satisfactory results which indicates the rationality and feasibility of the design of the integrated high Q inductor embedded in PI.