The Challenges of Wafer Blade Dicing by Minimize Die Size

Wafer sawing is an essential and critical process in semiconductor manufacturing. After the development of the industry, wafer dicing has shown diversification, mainly including laser cut (laser grooving or laser stealth cutting), plasma dicing and blade dicing etc. For silicon (Si) wafer dicing, the process defects of laser cut (such as chipping/crack) are better than traditional blade dicing, but the cost is higher; Plasma dicing can achieve no chipping and crack issues, but the running costs are also high, and the wafer design has special requirements for saw-lane. Blade dicing causes chipping due to mechanical stress, but the cost is low, and the technology is mature in normal Si wafer, so it is still widely used. Therefore, in the practical application process, considering the investment of operating costs and quality, silicon wafer dicing tends to focus on traditional blade dicing. With the continuous innovation and technological breakthrough of science and technology, the semiconductor industry has been widely used, promoting the rapid development of the industry. Also, the change of market environment, product market competition is more and more fierce, need to improve product cost performance. Reducing die size to increase die quantity per wafer is a way to cost down. So, wafer fabrication houses continuously face challenges in manufacturing semiconductor devices because the devices continue to get tinier and more complicated. For wafer dicing, also has challenges once die size too small, especially blade dicing because the blade dicing will be limitations, such as die chipping & die shift or fly die and so on. This paper will be focusing on developing appropriate dicing blade type, dicing tape and dicing parameters (spindle speed, feed rate etc). Find the best recipe for blade dicing. The challenge for newly introduced smaller die wafer is overcome, the die size is reduced from current W+50 um to W-10 um, the die quantity (Qty) per wafer increased 65%. This results in an around 40% cost saving in wafer manufacturing. Our process characterization includes 5 flows: (1) Feasibility study; (2) Pre-screen DOE (Design of experience); (3) Full DOE; (4) Validation run. Feasibility study is mainly to evaluate different degrees of viscous dicing tape and different dicing blades with different diamond granularity to preliminarily narrow the selection range. In pre-screen DOE, it is carried out with 2 types of dicing tapes and 3 different types of blades based on the feasibility study results. In full DOE, the key factors are selected from pre-screen DOE sawed in dicing study matrix. The collected data are analyzed by Minitab-a professional data processing software. Optimizing sawing parameters and identifying key factors from the data graph are essential to ensure precision. It is imperative to conduct verification experiments during validation run and final validation to validate these findings.